1. Field of Invention
This invention relates to improvements in circuit design methods, and more particularly to improvements in domino circuit design methods, and still more particularly to circuit libraries for use in performing such methods.
2. Relevant Background
Recently, circuit designers have been devoting increased interest to CMOS domino logic circuit designs, because of their reduced integrated circuit area, smaller parasitic capacitances, higher speed, and increased reliability.
Typically, domino logic circuits have an NMOS, or pull-down, logic portion, although PMOS pull-up logic circuits have been used in many applications. The logic portion serves to evaluate input logic signals to provide a conditional output signal to an output inverter.
Domino logic circuits also have a precharge transistor, typically a PMOS device when the logic circuit is made up with NMOS transistors, which is switched by the clock signal to connect the “dynamic node” of the circuit to a precharge voltage during a “precharge phase” of the clock cycle. The “dynamic node” may be for example, the output node of the logic circuit or the input node of the associated output inverter.
Thus, typically, the output inverter transistors are precharged during the precharge phase, while the clock signal is in a first state, low, for example, in an NMOS logic circuit implementation, or high in a PMOS logic circuit implementation. During the precharge phase, an “evaluate” transistor, whose gate is also connected to the clock signal, isolates the associated logic circuit from the precharge voltage.
When the particular logic conditions of the logic circuit are met during a subsequent “evaluate” phase when the clock signal transitions from low to high in the NMOS logic circuit implementation, the output node of the logic circuit (the input of the inverter) is pulled down and the output of the inverter is pulled up. If the logic conditions of the logic circuit are not met, the output of the inverter remains low. Because the inverter is precharged when the clock signal transitions from low to high, the cell output can be developed very rapidly.
In the design of domino logic circuits, it will be appreciated that different applications require circuits of different speeds and driving abilities. However, usually a trade-off is involved, since in domino logic applications, usually faster circuits are larger in layout size, and consequently occupy more real estate of the substrate on which the circuit is constructed, and additionally consume more power. On the other hand, if the transistors of the logic circuit are made too large, they may unduly load the driver circuit. Consequently, in some applications, it may be that the driver circuit is large, while the associated logic circuitry is of relatively smaller devices, or vice versa. It can be seen that depending upon the particular application, large numbers of combinations of circuits may be required.
As a result, domino logic circuits had to be individually designed to provide the necessary speed and drive power for a particular application. However, once the drive circuit has been designed, the associated logic circuit also had to be designed in accordance with the parameters of the drive circuit (or vice versa). As can be seen, this design process has been difficult and time consuming.
In efforts to standardize the design process, layout templates have been proposed into which the various domino circuit components can be placed in order to facilitate interconnection of a number of gates in a particular circuit. The arrangement of the various circuit parts in fixed layout regions provides a “standard cell”, connectable to similar adjacent regions.
In one proposal, for example, a layout template is suggested for a domino logic circuit of the type having an n-FET logic tree. The n-FET logic tree is inserted into a first portion of the template. The output from the logic circuit is inverted in an output inverter, and latched by a p-FET device connected around the inverter. The p-FET portions of the inverter, a p-FET precharge transistor, and the p-FET latch transistor are inserted in predefined second template locations. The clock also includes an n-FET evaluate transistor, which is inserted into a third template area.
However, in this and other previous proposals, the fixed layout template has not been concerned with the parametric characteristics of the ultimate cells, only the standardization of the layout template into which they are constructed to enable standardization of cell interconnections.
What is needed, therefore, is a method and circuit library for designing domino logic circuits to form a collection of domino logic cells that can be used for particular applications having varying drive power and speed requirements.